After completing the module, the students know how to customize and optimize a processor architecture (instruction, data and task level parallelism). They are capable of implementing application-specific instruction set processors (ASIPs). They can implement arithmetic-oriented hardware extensions and know new development tendencies of processors, e.g., highly parallel processors and reconfigurable processors.
Code | 4211033 + 4211034 |
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Degree programme(s) | Computer and Communication Systems Engineering |
Lecturer(s) | Prof. Guillermo Payá Vayá |
Type of course | Lecture + exercise course |
Semester | Summer semester |
Language of instruction | English |
Level of study | Master |
ECTS credits | 5 |
Contact person | Marvin Plagge |