LPDP - TU Braunschweig Promotionsstipendien

Explore how micro-LEDs change our ideas of computing, sensing and chip design and build the next generation of intelligent chips.

Starting in September

Months Scholarship Duration

Proposed Research Topics

Why TU Braunschweig?

Wissenschaftlerin im LENA Forschungszentrum

From semiconductor materials to intelligent systems

Develop your expertise in a research environment that brings together materials, devices, chip design and applications. Work across disciplines on technologies for more efficient computing, better sensing and new electronic and photonic systems.

Connect ideas with experiments

Combine modelling and design with fabrication, measurement and system development, according to your chosen project.

Research across disciplines

Learn from teams spanning engineering and physics, with connections to research institutes, industry and technology development.

Explore the research environment

Who can apply?

Indonesian citizens
Including CPNS/PNS/TNI/POLRI: civil servant candidates, civil servants, members of the armed forces and police.

Maximum age: 47 years

Minimum GPA / IPK: 3.25

Minimum English scores
TOEFL iBT: 90/120 or IELTS: 6.5/9.

Doctoral admission
Candidates must also meet TU Braunschweig's academic admission requirements.

The LPDP call will provide the detailed eligibility rules, accepted evidence and document checklist.

Find the project that fits your strengths

Start with a research direction, then open a topic to explore its objectives, methods and supervisor. The catalogue contains 25 proposed projects across three research areas for the Starting September 2027.

Semiconductor Materials and Devices (7 Research Topics)

Integrated Circuits and Computing Architectures (9 Research Topics)

Sensors and Electronic Systems (9 Research Topics)

Area 1: Semiconductor Materials and Devices

Supervisor: Prof. Dr. Tobias Voss, Nitride Technology Center and Institute of Semiconductor Technology, TU Braunschweig

Background and motivation

Two-dimensional semiconductors offer atomically thin, dangling-bond-free channels for scaled transistors, flexible devices and monolithic 3D integration. Monolayer molybdenum disulfide (MoS₂) combines a direct band gap and strong photoluminescence with sensitivity to its dielectric environment, making it attractive for electronic, optoelectronic and sensor applications. Reliable electrical contacting remains a key challenge: metal deposition can introduce defects, Fermi-level pinning and strain, reducing performance and reproducibility.

Research objectives

Develop a robust and reproducible fabrication process for electrically contacted MoS₂ monolayers, operate the contacted structures as field-effect transistors, and establish correlations between the optical and electrical properties of the devices. The work will create the technological foundation for MoS₂-based FETs in next-generation electronic and sensor systems with combined optical and electrical readout.

Approach and methods

1. Prepare MoS₂ monolayers by mechanical exfoliation and chemical vapour deposition (CVD) and transfer them onto suitable substrates. Pattern contact geometries by maskless laser lithography, followed by metallization and lift-off, to realize FET structures with gate, source and drain.

2. Investigate and compare different contacting strategies: suspended (freestanding) MoS₂ monolayers, h-BN-encapsulated structures, and variants employing different contact metals or interlayers such as graphene, targeting low contact resistance and high reproducibility.

3. Characterize the fabricated devices electrically and optically. Current–voltage and gate transfer/output measurements provide contact resistance, carrier mobility, threshold voltage and subthreshold behaviour, while photoluminescence and Raman spectroscopy analyse material quality, strain and doping. Correlate both measurement modalities on identical devices.

Expected outcomes

The expected outcomes are a robust, reproducible contacting process for MoS₂ monolayer FETs, a systematic comparison of the contacting strategies with their impact on device performance, and a validated methodology for correlated optical–electrical characterization. The work will provide the technological foundation for MoS₂-based sensors in which optical and electrical signals are combined to detect molecular interactions at the surface of the 2D material.

Suggested candidate profile

A background in electrical engineering, physics, microelectronics or a related discipline would be suitable. Interest in semiconductor technology, cleanroom processing (lithography, thin-film deposition) and optoelectronic characterization is mandatory. Further interest in 2D materials, nanofabrication, device physics and optical spectroscopy would support the project.

Research connections

Supervisor: Prof. Dr. Tobias Voss, Nitride Technology Center and Institute of Semiconductor Technology, TU Braunschweig

Background and motivation

Conductive poly(3,4-ethylenedioxythiophene) (PEDOT) combines electrical conductivity, optical transparency, flexibility and low-temperature processing. Oxidative chemical vapour deposition (oCVD) forms conformal, pinhole-free PEDOT films directly from the vapour phase, avoiding limitations of liquid-processed PEDOT:PSS. The group has demonstrated a compact EDOT/SbCl₅ reactor and photoresist-based lift-off of 10 µm stripes with negligible conductivity loss and record-low PEDOT/metal contact resistivities. This project investigates patterning and contacting at smaller scales while preserving electrical performance.

Research objectives

Develop lithography-based patterning and contacting processes for oCVD PEDOT that extend the lateral feature size from the 10 µm demonstrated so far down to a few hundred nanometers, while preserving the high electrical conductivity of the as-deposited layers and the low contact resistivity of the PEDOT/metal interface. The work will create a validated process module that integrates vapor-deposited conductive polymers into the microelectronics fabrication toolbox.

Approach and methods

1. Deposit optimised oCVD PEDOT films using EDOT/SbCl₅ chemistry on silicon oxide and other relevant substrates, with growth rates down to a few nm/min and conductivities up to approximately 500 S/cm.

2. Develop electron-beam lithography down to a few hundred nanometres. Identify compatible resists, developers, bake temperatures and process steps, and quantify their electrical impact.

3. Develop maskless laser lithography for micrometre-scale structures and compare resolution, edge quality and throughput with the electron-beam route.

4. Optimise metal contacts, adhesion layers and interlayers in multistep “PEDOT first” and “PEDOT last” processes, targeting low contact resistivity at sub-micrometre geometries.

5. Use transfer-length and four-point-probe measurements to quantify size-dependent conductivity. Use AFM and Raman spectroscopy to assess edge quality, polymer integrity and doping, and identify process-induced degradation.

Expected outcomes

The expected outcomes are electron-beam and laser lithography processes for the lateral structuring of oCVD PEDOT from a few micrometers down to a few hundred nanometers, a quantitative understanding of the size-dependent conductivity and contacting behaviour of patterned PEDOT, and design rules for conductivity-preserving microfabrication. The work provides a process module for conductive polymer components in microelectronic devices such as transparent electrodes, organic transistors, and (bio-)chemical sensors.

Suggested candidate profile

A background in electrical engineering, physics, microelectronics, materials science or a related discipline would be suitable. Relevant interests include semiconductor processing, conductive polymers and device physics. Familiarity with cleanroom fabrication, lithography, electrical measurements or optical characterisation would support the work.

Research connections

Supervisor: Prof. Dr. Stefanie Kroker, TU Braunschweig and Physikalisch-Technische Bundesanstalt (PTB)

Background and motivation

Spatial light modulators based on liquid crystals switch at kilohertz rates and use pixels of several micrometres. This limits applications such as free-space optical communication, solid-state LiDAR and the individual addressing of trapped ions or neutral atoms in quantum computers. Electro-optic metasurfaces exploit the Pockels effect in thin films of lithium niobate, barium titanate or organic electro-optic materials. Nonlocal high-Q resonances enhance the small index change, and free-space modulation at gigahertz rates has recently been demonstrated. Current devices still require drive voltages of several volts or more, are limited by their RC time constant to around one gigahertz and mostly operate as single pixels. Recent work identifies pixelation and drive voltages compatible with CMOS electronics as the next steps towards practical devices.

Research objectives

Develop pixelated electro-optic metasurface modulators that combine gigahertz bandwidth with drive voltages suitable for CMOS driver circuits, and derive co-design rules linking optical resonance, electrode layout and driver electronics.

Approach and methods

1. Design nonlocal high-Q metasurfaces on thin-film lithium niobate or barium titanate using coupled-mode theory and full-wave simulations. Include finite-aperture effects, which set the minimum pixel size and the optical crosstalk between neighbouring pixels.

2. Co-design electrodes and the electrical equivalent circuit of each pixel. Compare metallic interdigitated electrodes with low-loss doped-semiconductor or transparent conducting electrodes. Quantify the trade-off between pixel capacitance, optical loss, bandwidth and voltage swing.

3. Fabricate devices on commercially available thin-film wafers by electron-beam lithography and dry etching. Characterise them by DC spectroscopy, vector network analysis and data-transmission experiments. Demonstrate a one-dimensional array of independently driven pixels for beam steering or multi-channel modulation at telecom wavelengths and assess the transfer to visible wavelengths relevant for atomic qubits.

Expected outcomes

The project aims at a pixelated electro-optic metasurface demonstrator with measured bandwidth, modulation efficiency per volt and inter-pixel crosstalk. Design guidelines will show which combinations of resonance, electrode concept and pixel size allow direct operation from CMOS drivers.

Suggested candidate profile

A background in electrical engineering, physics, photonics or microelectronics would be suitable. Relevant preparation includes electromagnetics, semiconductor technology and high-frequency measurement techniques. Interest in numerical simulation, nanofabrication in a cleanroom and optical characterisation would support the work.

Research connections

Supervisor: Prof. Dr. Stefanie Kroker, TU Braunschweig and Physikalisch-Technische Bundesanstalt (PTB)

Background and motivation

Many applications of reconfigurable optics need a stable configuration rather than continuous modulation, for example adaptive beam shaping, programmable lenses or optical weights in analogue and neuromorphic optical processors. Volatile tuning mechanisms such as liquid crystals, carrier injection or the Pockels effect consume power to hold a state. Low-loss chalcogenide phase-change materials such as Sb2Se3 and Sb2S3 switch between amorphous and crystalline phases with a large refractive-index contrast and retain their state without power. Electrical switching by integrated microheaters has been demonstrated, and first pixelated devices have been reported. Recent reviews name scalable pixel addressing, thermal crosstalk, endurance and reliable multilevel programming as the main open issues. These questions closely resemble those of phase-change memory in microelectronics.

Research objectives

Develop electrically programmable, non-volatile phase-change metasurfaces with individually addressable pixels. Treat the pixel array as an optical memory with defined write, read and retention characteristics.

Approach and methods

1. Design Sb2Se3 or Sb2S3 metasurfaces on silicon or silicon nitride with integrated doped-silicon or transparent conducting microheaters. Use coupled electro-thermal and optical simulations of amorphisation and crystallisation, including thermal crosstalk between pixels.

2. Develop a row–column addressing scheme with selector elements and pulse-shaping driver electronics, adapting concepts from phase-change memory arrays. Investigate multilevel programming by partial crystallisation with closed-loop optical verification.

3. Fabricate and characterise pixel arrays with respect to switching energy, optical contrast, endurance, retention and drift. Demonstrate a reprogrammable optical function such as beam steering, a varifocal lens or a reconfigurable matrix of optical weights.

Expected outcomes

The intended result is an addressable phase-change metasurface demonstrator with measured reliability figures. The work will provide design rules relating pixel pitch, heater geometry and addressing scheme to thermal crosstalk and switching energy, and will assess the use of such arrays in low-power optical computing.

Suggested candidate profile

A background in microelectronics, electrical engineering, materials science or physics would be suitable. Relevant preparation includes semiconductor technology, thin-film deposition and electrical or thermal device modelling. Interest in non-volatile memory devices, nanophotonics and experimental characterisation would support the project.

Research connections

Supervisor: Prof. Dr. Andreas Waag, Nitride Technology Center and Institute for Semiconductor Technology, TU Braunschweig

Background and motivation

Photonic crystal surface emitting lasers combine high optical power and good beam quality in a compact semiconductor chip. Nitride materials provide access to ultraviolet and visible wavelengths, supporting applications in optical computing, lidar ranging and high-power light sources. Their performance depends on the interaction between epitaxial material quality, photonic-crystal geometry and device processing.

Research objectives

Develop nitride photonic crystal surface emitting lasers by linking epitaxial growth with nanofabrication, processing and optical characterization. Establish how material and structural choices affect laser operation and the suitability of the devices for integrated optical systems.

Approach and methods

1. Investigate epitaxial growth of nitride laser structures and characterize material quality and optical properties.

2. Develop photonic-crystal fabrication and device-processing approaches compatible with the selected nitride structures.

3. Characterize emission, beam quality and device behaviour, relating the results to growth and fabrication choices.

4. Use feedback between material growth and device characterization to refine the laser platform.

Expected outcomes

The research should provide characterized nitride laser structures, a reproducible fabrication approach and experimentally supported relationships between material quality, photonic-crystal design and laser performance. These results will support the selection of light sources for optical computing and other applications requiring compact, well-controlled emission.

Suggested candidate profile

A Master’s degree in electrical engineering, physics, materials science or a related field is appropriate. Interests in semiconductor epitaxy, cleanroom fabrication, laser physics and experimental optical characterization would support the project.

Research connections

Supervisor: Prof. Dr. Andreas Waag, Nitride Technology Center and Institute for Semiconductor Technology, TU Braunschweig

Background and motivation

Trapped-ion quantum computers require precisely controlled ultraviolet and visible light at multiple locations. Bringing optical functions onto a chip can reduce the dependence on separate free-space components and support more scalable delivery of light to qubits. Nitride photonic platforms offer a route to integrated waveguides and components at these wavelengths.

Research objectives

Develop low-loss nitride waveguides and integrated photonic components for delivering controlled ultraviolet and visible light to trapped-ion qubits. Investigate how component design, fabrication and optical characterization can support reliable light distribution on a chip.

Approach and methods

1. Define optical requirements for chip-based light delivery to trapped-ion quantum systems.

2. Design nitride waveguides and photonic components for operation at relevant ultraviolet and visible wavelengths.

3. Fabricate and characterize test structures, examining propagation loss and component performance.

4. Use experimental feedback to improve the photonic platform and assess routes towards integration in quantum-computing systems.

Expected outcomes

Expected outcomes include characterized nitride waveguides and photonic components, design and fabrication guidance, and an assessment of their suitability for controlled optical delivery to trapped ions. The research will establish relationships between fabrication choices and optical performance relevant to scalable quantum hardware.

Suggested candidate profile

A Master’s degree in electrical engineering, physics, materials science or a related discipline is appropriate. Preparation in integrated optics, semiconductor fabrication or optical characterization would be useful, together with interest in quantum technologies.

Research connections

Supervisor: Markus Etzkorn, Institute of Applied Physics, TU Braunschweig

Background and motivation

Semiconducting quantum dots support electronic and quantum-optical devices, including single-photon sources, light-emitting structures and sensors. Their performance depends on nanoscale and atomic-scale composition, strain, interfaces and defects as well as size and shape. Structural feedback is therefore essential for understanding and improving epitaxial growth and optical behaviour.

Research objectives

Use advanced electron microscopy to correlate quantum-dot growth conditions, nanoscale structure, composition and optical response. Provide structural and spectroscopic feedback that supports targeted improvements in quantum-dot properties.

Approach and methods

1. Use scanning electron microscopy to measure dot-size distributions, surface morphology, spatial uniformity and local dot density across representative sample areas.

2. Use aberration-corrected transmission electron microscopy to investigate individual dots and the surrounding semiconductor matrix at atomic resolution.

3. Combine imaging with spectroscopic methods to examine elemental composition, interfaces, lattice strain and structural imperfections.

4. Correlate microscopy results with growth conditions and optical measurements, and provide feedback to semiconductor growth researchers.

Expected outcomes

The project should produce correlated microscopy, spectroscopy and optical datasets that explain how growth conditions influence quantum-dot structure and function. Expected outcomes include statistically supported morphological analysis, atomic-scale structural information and feedback that helps refine growth processes for quantum-light applications.

Suggested candidate profile

A background in physics, materials science, electrical engineering or a related field would be appropriate. Interest in electron microscopy, semiconductor nanostructures and quantitative image or spectroscopy analysis would support the research.

Research connections

Area 2: Integrated Circuits and Computing Architectures

Supervisor: Prof. Dr. Andrés Gómez, Robust Hardware and Software Systems, Institute of Computer and Network Engineering (IDK), TU Braunschweig

Background and motivation

Orbital edge computing moves data-intensive applications onto CubeSats so that sensor data can be processed on board rather than relayed to the ground. Snapshot Global Navigation Satellite System (GNSS) positioning and homomorphic computing are representative workloads. Commercial SRAM-based field-programmable gate arrays (FPGAs) offer an accessible platform, but their configuration memory and user logic are susceptible to radiation-induced single-event upsets. Uniform triple modular redundancy with scrubbing can impose substantial area, power and latency costs.

Research objectives

Develop workload-aware fault tolerance for commercial FPGAs used in CubeSats, adjusting protection to the needs of the application and the constraints of the on-board platform.

Approach and methods

1. Build on open-source RISC-V fault-tolerant intellectual property to provide configurable protection for processors, memories and hardware accelerators.

2. Co-design protection that can be adjusted at run time with configuration scrubbing and dynamic partial reconfiguration.

3. Use snapshot GNSS positioning and homomorphic computing as case studies. Quantify soft-error resilience and the associated area, power and latency overheads through fault-injection campaigns and proton-beam tests.

Expected outcomes

An open-source reference design and a ground-validated demonstrator are expected. The evaluation will show how workload-aware protection changes the balance between soft-error resilience and implementation overheads for CubeSat computing.

Suggested candidate profile

A background in computer engineering, electrical engineering or a related field would be suitable. Relevant preparation includes digital hardware design, FPGA development and embedded systems. Interest in RISC-V architectures, hardware reliability and hardware–software co-design would support the work.

Research connections

Supervisor: Prof. Dr.-Ing. Guillermo Payá Vayá, Chip Design for Embedded Computing, TU Braunschweig

Background and motivation

Snapshot Global Navigation Satellite System (GNSS) positioning is a demanding application for orbital edge computing. CubeSat processors must operate within tight power budgets while tolerating radiation. Radiation-hardened processors are expensive, whereas commercial SRAM-based FPGAs expose configuration memory to single-event upsets. Application-specific instruction-set processors (ASIPs) offer an alternative that trades some flexibility for energy efficiency.

Research objectives

Develop a hardened, low-power ASIP for on-board snapshot GNSS, using the RISC-V-based V2PRO vertical vector processor as the architectural starting point.

Approach and methods

1. Develop custom vector instructions and datapath extensions for correlation- and FFT-dominated kernels used in satellite acquisition and position solving. Co-design the extensions with the V2PRO software toolchain.

2. Apply radiation hardening by design to memories, register files and critical datapaths through error detection and correction.

3. Use adaptive body biasing in 22 nm FD-SOI technology to reduce power. Aim to tape out the ASIP and evaluate soft-error resilience and energy efficiency through fault injection and irradiation campaigns.

Expected outcomes

The project aims to produce an ASIP chip and an evaluation of its energy efficiency and soft-error resilience. Its contribution is a coordinated processor, toolchain and hardening approach for snapshot GNSS under CubeSat power and radiation constraints.

Suggested candidate profile

A background in computer engineering, microelectronics or electrical engineering would be suitable. Processor architecture, RTL design and embedded programming are relevant foundations. Interest in signal processing, compiler support and reliable integrated circuits would support the project.

Research connections

Supervisor: Prof. Dr. Thomas Kämpfe, Institute of Neuromorphic Computing, TU Braunschweig

Background and motivation

Most neuromorphic chips are trained offline and perform inference without adapting to sensor drift, new classes or changing environments in the field. Ferroelectric devices offer analogue, non-volatile and low-energy weight updates, making them attractive for learning directly on the chip. Their switching physics also introduces asymmetric and stochastic updates and limited precision, which must be considered when designing learning rules.

Research objectives

Investigate local learning rules compatible with hafnia-based ferroelectric synapses and demonstrate a path from device physics to adaptive, self-calibrating intelligence at the edge.

Approach and methods

1. Study spike-timing-dependent plasticity, surrogate-gradient and three-factor learning rules in relation to the switching behaviour of ferroelectric synapses.

2. Develop a device-aware learning framework and map it onto a mixed-signal neuromorphic core architecture.

3. Implement a small-scale test chip with ferroelectric synaptic arrays and on-chip plasticity circuits. Evaluate continual learning on sensor streams such as audio, vibration and biosignals within a power budget suitable for battery-powered or energy-harvesting devices.

Expected outcomes

Expected outcomes include a device-aware learning framework, a mixed-signal implementation and a small-scale test chip. The evaluation will connect the behaviour of ferroelectric weight updates to continual-learning performance and the power needs of adaptive sensor systems.

Suggested candidate profile

A background in microelectronics, electrical engineering, computer engineering or a related discipline would be suitable. Relevant interests include neuromorphic computing, mixed-signal circuits and machine learning. Familiarity with semiconductor devices or device modelling would help connect the learning rules to ferroelectric switching physics.

Research connections

Supervisor: Prof. Dr. Thomas Kämpfe, Institute of Neuromorphic Computing, TU Braunschweig

Background and motivation

Condition monitoring of machines, infrastructure and the environment requires continuous analysis of sensor data. Many sensing nodes are battery-powered or energy-autonomous and cannot support conventional processors or continuous wireless transmission of raw data. Spiking neural networks (SNNs) offer an approach to sparse, event-based processing close to the sensor.

Research objectives

Design an always-on application-specific integrated circuit (ASIC) that detects anomalies in vibration, acoustic or electrical signals locally at microwatt power levels and transmits only events.

Approach and methods

1. Develop event-based signal encoding and sparse SNN architectures for sensor anomaly detection. Use non-volatile ferroelectric storage for network weights.

2. Carry the architecture through digital or mixed-signal circuit implementation and tape-out in a commercial CMOS technology.

3. Evaluate predictive-maintenance and infrastructure-monitoring benchmarks, focusing on hardware-efficient unsupervised detection and robustness to previously unseen fault types. Measure energy per inference in silicon.

Expected outcomes

The intended result is a silicon-proven anomaly-detection core with measured energy per inference. A methodology for mapping SNNs onto resource-constrained hardware will support applications in industrial IoT, agriculture and remote environmental monitoring.

Suggested candidate profile

A background in microelectronics, electrical engineering or computer engineering would be suitable. Relevant preparation includes digital or mixed-signal circuit design, embedded signal processing and neural networks. Interest in event-based sensing and low-power ASIC implementation would support the research.

Research connections

Supervisors: Prof. Dr. Thomas Kämpfe, Institute of Neuromorphic Computing, TU Braunschweig / Prof. Dr. Guillermo Payá Vayá, Chip Design for Embedded Computing, TU Braunschweig

Background and motivation

Compute-in-memory (CIM) based on hafnium-oxide ferroelectric field-effect transistors (FeFETs) combines non-volatile weight storage with CMOS compatibility. It is a promising approach for energy-efficient edge AI, but many demonstrations stop at the macro level. System integration requires coordinated treatment of device variability, processor interfaces and software mapping.

Research objectives

Integrate FeFET CIM macros as tightly coupled accelerators in an open-source RISC-V system-on-chip (SoC), connecting network mapping to physical implementation and silicon evaluation.

Approach and methods

1. Develop behavioural and variability-aware models of the CIM macro. Define memory-mapped and instruction-set-extension interfaces to the RISC-V system.

2. Extend compiler and runtime support for quantised convolutional and spiking neural networks mapped onto the macro.

3. Implement the design in a 22 nm FDSOI technology with a ferroelectric option. Cover RTL design, physical implementation, tape-out and silicon evaluation using workloads such as keyword spotting and sensor anomaly detection.

Expected outcomes

Expected outcomes are an end-to-end demonstrator with measured energy per inference, an open tool flow for CIM-accelerated RISC-V systems, and design guidelines for jointly optimising device non-idealities and architecture.

Suggested candidate profile

The project is suited to candidates with a background in microelectronics or computer engineering. It combines device-level understanding with digital chip design. Preparation in RTL design, processor architecture, modelling or compiler-supported acceleration would be relevant.

Research connections

Supervisor: Prof. Dr.-Ing. Guillermo Payá Vayá, Chip Design for Embedded Computing, TU Braunschweig

Background and motivation

Autonomous point-of-care and implantable monitoring systems need digital processing that fits stringent energy constraints. A processor dedicated to biomedical workloads can complement an analogue sensor front-end by performing signal conditioning, feature extraction and lightweight classification on the device. Compatibility with the RISC-V ecosystem provides access to an open-source software toolchain.

Research objectives

Develop an ultra-low-power application-specific instruction-set processor for biomedical signal processing in GlobalFoundries 22 nm FDSOI and/or 12 nm LP technology.

Approach and methods

1. Build on a RISC-V-compatible core and add domain-specific instructions for real-time signal conditioning, feature extraction and lightweight classification. Example workloads include glucose trends, pH, dehydration and ECG/EEG features.

2. Maintain compatibility with the open-source RISC-V toolchain while optimising area and power for the selected biomedical workloads.

3. Investigate a multi-cycle datapath with fine-grained clock gating and near-threshold voltage operation. Exploit reverse body biasing at circuit level when using FDSOI technology.

Expected outcomes

The intended result is an application-specific processor architecture that serves as the digital companion to biomedical analogue front-end circuits. The work will connect instruction-set choices and datapath organisation to energy-efficient processing of physiological signals.

Suggested candidate profile

A background in computer engineering, microelectronics or electrical engineering would be suitable. Relevant preparation includes processor architecture, RTL design and embedded programming. Interest in biomedical signal processing, RISC-V toolchains and low-power circuit techniques would support the work.

Research connections

Supervisor: Prof. Dr.-Ing. Guillermo Payá Vayá, Chip Design for Embedded Computing, TU Braunschweig

Background and motivation

Hearing aids and wearable audio devices need continuous signal processing within a small battery budget. Domain-specific audio processing can be combined with neural-network acceleration to support adaptive processing. The earlier KAVUAKA hearing-aid processor in 65 nm technology provides a starting point for an architecture implemented in a more advanced CMOS node.

Research objectives

Develop an ultra-low-power audio processor with an on-chip neural-network accelerator in GlobalFoundries 22 nm FDSOI and/or 12 nm LP technology, targeting hearing-aid and wearable applications.

Approach and methods

1. Extend the KAVUAKA architecture with an audio datapath for workloads such as real-time beamforming, noise reduction, speech enhancement and equalisation.

2. Integrate a neural-network accelerator for adaptive audio processing, including possible neural-network-based noise suppression, speech classification and scene-aware gain control.

3. Investigate fine-grained clock gating, near-threshold operation or FDSOI reverse body biasing. Target a complete audio SoC with an analogue microphone front-end, digital audio processor, neural-network accelerator and wireless interface, operating autonomously from a coin-cell battery.

Expected outcomes

The intended outcome is an audio-processing architecture that combines dedicated signal processing with on-chip neural-network acceleration. The integration target is a complete autonomous audio SoC suited to the energy constraints of hearing aids and wearable devices.

Suggested candidate profile

A background in computer engineering, microelectronics or electrical engineering would be suitable. Relevant preparation includes digital chip design, processor architecture and audio signal processing. Interest in neural-network acceleration and low-power embedded systems would support the project.

Research connections

Supervisor: Prof. Dr. Andreas Waag, Nitride Technology Center and Institute for Semiconductor Technology, TU Braunschweig

Background and motivation

The energy demand of artificial intelligence motivates alternative computing hardware. Optical neuromorphic processors use light to implement neural-network operations, requiring light sources, modulation and photonic interconnections that work together efficiently. Nitride semiconductors offer building blocks for integrated ultraviolet and visible photonic circuits.

Research objectives

Develop nitride-based light sources, modulators and integrated photonic circuits as building blocks for optical neuromorphic computing. Establish how their optical and electrical characteristics affect their use in an optical neuromorphic computing core.

Approach and methods

1. Identify component functions and interface requirements for the optical computing architecture.

2. Design and develop nitride light sources, modulators and photonic circuit elements suited to those functions.

3. Fabricate and characterize component structures, relating fabrication and operating conditions to optical performance.

4. Evaluate component combinations and their compatibility with electronic control and system integration.

Expected outcomes

The intended outcomes are characterized photonic building blocks, design guidance and experimental evidence of their suitability for optical neural-network hardware. The work will clarify component limitations and integration requirements, providing a basis for the development and evaluation of an optical neuromorphic computing core.

Suggested candidate profile

A Master’s degree in electrical engineering, physics, materials science or a related field is appropriate. Relevant interests include semiconductor optoelectronics, integrated photonics, fabrication and experimental characterization, with curiosity about computing hardware.

Research connections

Supervisor: Prof. Dr. Andreas Waag, Nitride Technology Center and Institute for Semiconductor Technology, TU Braunschweig

Background and motivation

An optical neuromorphic computing core requires electronic control and software interfaces before it can be used within conventional AI and high-performance computing environments. Drivers, readout, timing and data movement influence the practical benefits of the optical hardware. System integration therefore connects photonic devices with digital hardware and computing software.

Research objectives

Integrate optical neuromorphic processors with electronic control and established AI and high-performance computing infrastructure. Develop and assess the hardware and software interfaces needed to operate the optical core and benchmark complete workloads.

Approach and methods

1. Develop driver and readout electronics, FPGA-based control and high-speed interfaces between the optical processor and conventional hardware.

2. Implement firmware, device drivers and real-time control for configuring and operating the optical computing core.

3. Develop software interfaces that connect the processor with common AI frameworks and high-performance computing environments.

4. Benchmark representative workloads against established hardware, accounting for interface, control and data-transfer overheads.

Expected outcomes

Expected outcomes include an integrated hardware and software environment for an optical neuromorphic processor, reusable control and interface modules, and a documented benchmarking workflow. Evaluation will identify how system overheads affect practical performance and guide integration with conventional computing infrastructure.

Suggested candidate profile

A Master’s degree in computer engineering, computer science, electrical engineering or a related discipline is appropriate. Relevant preparation includes digital hardware, embedded programming, software interfaces or AI computing systems, with interest in work across hardware and software.

Research connections

Area 3: Sensors and Electronic Systems

Supervisors: Prof. Dr. Thomas Kämpfe and Prof. Dr. J. Daniel Prades, TU Braunschweig

Background and motivation

Nanostructured metal-oxide chemiresistive gas sensors can be activated by micro-LED light instead of heating, reducing their power demand by orders of magnitude. Practical deployment remains limited by drift, cross-sensitivity and repeated recalibration, which currently relies on cloud-based machine learning. Local adaptive processing could address these constraints in distributed sensing systems.

Research objectives

Develop an electronic nose that converts sensor-array outputs directly into spike events and classifies them using an adaptive on-chip SNN with ferroelectric synapses, targeting in-situ learning and drift compensation below one milliwatt.

Approach and methods

1. Design the spike-encoding front-end and neuromorphic classifier for a light-activated nanomaterial gas-sensor array.

2. Co-optimise sensor operating modes with the learning algorithm so that sensing and adaptation can operate within the intended power budget.

3. Integrate the sensor platform and a custom ASIC into a compact module. Validate the module in air-quality, agricultural and food-spoilage monitoring scenarios.

Expected outcomes

The intended outcome is a compact sensor and ASIC module that combines local gas classification, adaptation and drift compensation at a sub-milliwatt power budget. Evaluation across the proposed monitoring scenarios will establish the connection between sensor operation and adaptive classification.

Suggested candidate profile

A background in electrical engineering, microelectronics, sensor technology or a related field would be suitable. The work bridges nanomaterial gas sensors, mixed-signal circuit design and embedded machine learning. Interest in neuromorphic processing and experimental sensor validation would be relevant.

Research connections

Supervisor: Prof. Dr. Vadim Issakov, Institute for CMOS Design, TU Braunschweig

Background and motivation

Point-of-care and implantable biomedical devices require highly integrated sensor interfaces that operate with low power consumption. Multiparameter systems may monitor quantities related to glucose, dehydration or pH. Integrating analogue and mixed-signal building blocks within advanced CMOS processes provides a route to compact sensing systems.

Research objectives

Develop highly integrated, low-power CMOS readout circuits for biomedical applications, using GlobalFoundries 22 nm FDSOI and/or 12 nm LP technology.

Approach and methods

1. Investigate sensor-readout circuits for point-of-care devices, with implantable multiparameter measurement systems as a potential application.

2. Develop the analogue and mixed-signal building blocks needed for a highly integrated implementation. The proposed scope includes low-dropout regulators, analogue-to-digital converters, mixers, phase shifters and oscillators.

3. Address integration with a fully integrated phase-locked loop, a power amplifier and on-chip antennas, as appropriate to the selected biomedical sensing system.

Expected outcomes

The intended outcome is a highly integrated low-power readout solution for biomedical sensing. The proposed building blocks establish the analogue part of an autonomous system, acquiring and conditioning sensor signals for subsequent processing.

Suggested candidate profile

A background in electrical engineering or microelectronics would be suitable, with preparation in analogue CMOS design and mixed-signal integrated circuits. Interest in sensor interfaces, biomedical instrumentation and circuit integration in advanced CMOS nodes would support the project.

Research connections

Supervisor: Prof. Dr. Vadim Issakov, Institute for CMOS Design, TU Braunschweig

Background and motivation

Biomedical microfluidic systems can use microelectromechanical systems (MEMS) to control liquid flow within microfluidic channels. Driving their electrodes requires integrated high-voltage circuits and programmable waveforms. Organ-on-chip systems are one potential application for this combination of electronic control and biomedical structures.

Research objectives

Develop a highly integrated high-voltage driver and arbitrary waveform synthesiser for controlling MEMS structures in biomedical applications.

Approach and methods

1. Design an array of high-voltage amplifiers to drive the electrodes of the selected MEMS structure.

2. Develop a waveform generator integrated on the same chip and programmable externally through a serial peripheral interface (SPI).

3. Use an advanced LDMOS process, such as GlobalFoundries BCD55 or XFAB XT018. Integrate the CMOS chip with the biomedical structure and demonstrate its operation with the MEMS device in the laboratory.

Expected outcomes

The expected result is an integrated driver and programmable waveform-generation solution, demonstrated with a MEMS device. Laboratory integration will connect the high-voltage CMOS circuits to the intended microfluidic control function.

Suggested candidate profile

A background in electrical engineering or microelectronics would be suitable. Relevant preparation includes analogue integrated-circuit design, high-voltage electronics and circuit simulation. Interest in MEMS interfaces, programmable waveform generation and laboratory validation of biomedical systems would support the work.

Research connections

Supervisor: Prof. Dr. Vadim Issakov, Institute for CMOS Design, TU Braunschweig

Background and motivation

Complex impedance measurement in implantable or encapsulated environments requires accurate signal generation and a sensitive receiver. A highly integrated implementation must coordinate excitation, signal conditioning and conversion while supporting autonomous operation. These requirements motivate the development of analogue and mixed-signal circuits in advanced CMOS nodes.

Research objectives

Develop a highly integrated CMOS complex impedance analyser for implantable or encapsulated environments, including the excitation and receive chains required for autonomous operation.

Approach and methods

1. Design an accurate sinusoidal signal generator with stepped frequency and phase. Filter its output through a chain of active filters and convert the signal into a differential current.

2. Develop the receiving chain, including a transconductance stage, chopping stages for noise reduction, variable-gain amplifiers and active filters.

3. Design analogue-to-digital converters with noise shaping and integrate the circuits in advanced CMOS technology for fully autonomous operation.

Expected outcomes

The intended result is an integrated complex impedance analyser combining controlled excitation with low-noise reception and analogue-to-digital conversion. The research will address the circuit blocks needed to make this measurement function available in an autonomous implantable or encapsulated system.

Suggested candidate profile

A background in electrical engineering or microelectronics would be suitable. Analogue and mixed-signal CMOS design are relevant foundations. Interest in low-noise circuits, data converters, active filters and impedance-based instrumentation would support the project.

Research connections

Supervisor: Prof. Dr. Tobias Voss, Nitride Technology Center and Institute for Semiconductor Technology, TU Braunschweig

Associated partners: Prof. Dr. J. Daniel Prades and Prof. Dr. Michael Kurrat

Background and motivation

Microelectronic sensing and readout technologies can help monitor battery performance and lifetime. Internal current uniformity depends on electrode microstructure, additives and surface functionalisation, but existing microscopic methods mainly examine the surface. Flexible microstructured contact arrays offer spatially resolved boundary measurements that could support reconstruction of the three-dimensional current distribution within an electrode.

Research objectives

Develop flexible microstructured electrode arrays for graphite anodes and a machine-learning model linking surface and boundary measurements to internal current distributions. Co-design the electronic sensor platform and electrode interface for spatially resolved monitoring of battery cell performance.

Approach and methods

1. Characterise partners’ cylindrical graphite anodes, mapping surface morphology and local conductivity. Include information on additives and surface functionalisation as reference data.

2. Fabricate individually addressable microelectrodes on PET using thin-film deposition, photolithography and lift-off. Develop top-face and circumferential arrays, matching pitch and contact area to expected inhomogeneity scales. Address compliance, isolation and homogeneous contacting, and design and test selective-addressing electronics.

3. Measure spatially resolved boundary current–voltage characteristics under steady-state, time-resolved and temperature-dependent protocols. Quantify reproducibility and contact back-action on local current distributions.

4. Combine surface and boundary data in a machine-learning reconstruction model. Address the underdetermined inverse problem using physical constraints, including charge conservation and known material parameters, and systematically assess spatial resolution and reliability.

Expected outcomes

The expected outcomes are a microfabricated, mechanically compliant sensor platform based on flexible microstructured electrode arrays; a validated methodology for reconstructing internal 3D current distributions from non-invasive boundary measurements; and a quantitative identification of the structural and chemical factors governing current uniformity in graphite anodes. The work provides the technological foundation for microelectronics-based monitoring of battery cell performance, a key step towards predictive battery diagnostics, impedance-based sensing integrated into cell designs, and the co-design of electrode materials and electronic monitoring systems.

Suggested candidate profile

A background in electrical engineering, physics, microelectronics or a related discipline would be suitable. Relevant interests include microfabrication, sensor interfaces and electrical characterisation. Experience with data analysis, machine learning or physical modelling would support the reconstruction of internal current distributions. Interest in battery materials and electrochemistry would help connect the electronic platform to the application.

Research connections

Supervisor: Prof. Dr. Eduard Jorswieck, Institute for Communications Technology, TU Braunschweig

Research associate: Mr. Nils Hildebrandt, Institute for Communications Technology, TU Braunschweig

Background and motivation

Future 6G wireless systems require flexible, energy-efficient radio-frequency (RF) front-ends that adapt their electromagnetic properties to changing communication environments. Reconfigurable intelligent surfaces (RIS), pixel-based antenna arrays and stacked intelligent metasurfaces (SIM) offer opportunities to shift signal-processing functions from power-hungry digital circuits towards programmable analogue hardware.

Research objectives

Investigate the joint design of microelectronic architectures and signal-processing algorithms for intelligent reconfigurable RF front-ends, accounting for realistic hardware constraints.

Approach and methods

1. Develop hardware-aware models and investigate energy-efficient circuit architectures for programmable electromagnetic structures.

2. Combine information-theoretic analysis, mathematical optimisation and electromagnetic modelling with circuit-level simulation. Experimental hardware implementations may also be considered.

3. Explore trade-offs between communication performance, circuit complexity, power consumption and reconfiguration capabilities. Use these trade-offs to guide the joint design of algorithms and RF hardware.

Expected outcomes

Expected outcomes include hardware-aware signal-processing algorithms, design guidelines for integrated reconfigurable RF architectures, and energy-efficient solutions for future wireless communication systems. The work will connect the behaviour of programmable electromagnetic structures to circuit constraints and communication performance.

Suggested candidate profile

A background in electrical engineering, communications, microelectronics or a related discipline would be suitable. Relevant preparation includes signal processing, mathematical optimisation and RF or electromagnetic modelling. Interest in linking communication theory with integrated-circuit design would support the interdisciplinary scope.

Research connections

Supervisor: Prof. Dr. J. Daniel Prades, Institute of Semiconductor Technologies, TU Braunschweig

Background and motivation

Multispectral chemical sensing requires compact semiconductor hardware that can acquire wavelength-dependent optical responses and deliver them efficiently to a computing system. CMOS detectors, wavelength-selective photodiodes and integrated optical filters offer routes to capture these signals without a bulky spectrometer. Coupling the resulting spatial and spectral data to an optical neuromorphic computing core requires coordinated detector, illumination and interface design. This project focuses on that semiconductor readout architecture, using established chemical-sensing layers as application test structures.

Research objectives

Develop a scalable semiconductor platform for multispectral optical readout of chemical sensor arrays and its interface to an optical neuromorphic computing core. Investigate detector architectures, spectral selectivity, illumination and signal conditioning to preserve useful chemical information with efficient acquisition and data transfer. Demonstrate the platform using established gas/VOC sensing layers, with environmental and water-quality sensing as possible extensions.

Approach and methods

1. Design and characterise a compact semiconductor multispectral readout using broadband white-LED illumination. Investigate wavelength-selective cascaded photodiodes, CMOS detector arrays and integrated or external tunable/fixed filters. Assess spectral response, crosstalk, noise and integration requirements, representing the measurements as a spatial-channel-by-spectral-band matrix.

2. Co-design optical acquisition, electronic readout and the input interface to an optical neuromorphic computing core. Develop calibration and reference-channel strategies, assess readout stability and drift, and evaluate timing, data representation and transfer requirements. Use conventional processing as a benchmark for the proposed interface.

3. Validate the readout and interface with established gas/VOC sensing layers and compare multispectral acquisition with RGB or intensity-only detection. Assess the contribution of the semiconductor platform to classification performance, interference tolerance and acquisition efficiency. The sensing layers provide test inputs; receptor synthesis and chemistry development are outside the project scope.

Expected outcomes

The intended result is a laboratory demonstrator of a semiconductor multispectral readout platform with an interface suitable for an optical neuromorphic computing core. Expected contributions include detector and filter architecture guidelines, characterised spectral and noise behaviour, calibration procedures and an experimentally validated acquisition-to-computing workflow. Tests using established chemical-sensing layers will assess how the platform preserves useful spectral information and supports classification. The work targets semiconductor integration and readout performance rather than the development of sensing receptor chemistries.

Suggested candidate profile

A background in electrical engineering, microelectronics, physics or a related discipline would be suitable. Relevant interests include semiconductor photodetectors, CMOS readout, photonics and experimental characterisation. Experience with optical measurements, electronic instrumentation, signal processing or embedded interfaces would support the work.

Research connections

Supervisor: Prof. Dr. J. Daniel Prades, Institute of Semiconductor Technologies, TU Braunschweig

Background and motivation

Conventional optical microscopes rely on bulky lens systems that limit their use in portable instruments and point-of-care environments. Lensless holography offers a compact alternative, but reflection arrangements can still require separate optical paths and complex alignment. In-line reflection holography places the sample above a reflective substrate so that the object and reference fields share a compact optical geometry. Combining GaN microLED illumination with silicon CMOS image sensors offers a route towards a robust, integrated reflection microscope.

Research objectives

Develop and validate a miniaturised reflection-holography microscope based on a reflective sample substrate, programmable GaN microLED illumination and a high-resolution CMOS detector. Establish the optical geometry, integration approach and computational reconstruction needed for reliable high-contrast imaging.

Approach and methods

1. Design and model the sample, reflective substrate and detector arrangement. Examine how sample-to-mirror spacing, illumination coherence and parasitic reflections affect the recorded interference signal and reconstructed image.

2. Develop a quasi-monochromatic microLED illumination module and optimise its positioning, spatial filtering and operating conditions for reflection holography.

3. Investigate heterogeneous integration and packaging of the GaN light source and silicon CMOS detector. Address optical access, alignment tolerances, stray light and mechanical stability.

4. Implement hologram acquisition, calibration and numerical reconstruction. Characterise contrast, reconstruction artefacts, repeatability and spatial resolution using suitable reference samples and compare with conventional microscopy.

Expected outcomes

The intended result is a laboratory demonstrator of an ultra-compact reflection-holography microscope with a validated illumination, mirror and detector geometry. The work will provide integration and calibration guidelines, a reconstruction workflow and an experimental assessment of image quality and mechanical robustness.

Suggested candidate profile

A background in electrical engineering, microelectronics, physics or a related discipline would be suitable. Relevant interests include optics, semiconductor integration and experimental instrumentation. Experience with image sensors, computational imaging, embedded systems or optical alignment would support the project.

Research connections

Supervisor: Prof. Dr. J. Daniel Prades, Institute of Semiconductor Technologies, TU Braunschweig

Background and motivation

Parallel optical instruments increasingly need to acquire images from multiple sensors while delivering programmable patterns to displays or microLED light engines. Independent camera and display pipelines can introduce timing uncertainty, repeated data transfers and bandwidth bottlenecks. MIPI camera and display interfaces provide established transport mechanisms, but a research instrument also needs coordinated triggering, buffering and control across all channels. A unified interface platform could make large optical input and output arrays easier to scale and integrate with computational imaging and optical neuromorphic hardware.

Research objectives

Develop an integrated multi-camera and display interface based on MIPI for scalable, synchronized image acquisition and parallel pattern generation. Co-design the data paths, timing architecture and software interface so that multiple optical channels can operate together with predictable latency and efficient use of memory and communication bandwidth.

Approach and methods

1. Define the system architecture around MIPI CSI-2 camera inputs and MIPI DSI/DSI-2 display outputs, selecting compatible devices and interface implementations. Distinguish the number of physical ports, transport channels and simultaneously active optical endpoints when assessing scalability.

2. Prototype an integrated FPGA or system-on-chip platform with camera reception, pattern generation, stream routing and buffering. Investigate local memory, direct memory access and host connectivity to reduce avoidable copying and data-transfer bottlenecks.

3. Develop a timing and synchronization layer linking camera exposure, display updates and illumination sequences. Address clock-domain crossings, timestamps, trigger distribution and buffering; measure alignment and latency instead of assuming that the transport protocols alone guarantee synchronization.

4. Implement firmware, drivers and a software interface for configuring channels, scheduling patterns, acquiring image batches and running closed-loop experiments. Validate parallel acquisition and generation using representative imaging or optical-computing workloads.

5. Evaluate sustained throughput, timing jitter, dropped-frame behaviour, data integrity, energy use and resource scaling. Derive architectural guidelines for increasing channel count and identify practical hardware and software bottlenecks.

Expected outcomes

The intended outcome is a working multi-camera and display interface demonstrator with coordinated timing, bidirectional image-data workflows and a documented control interface. The research will provide measured scaling and synchronization behaviour, reusable hardware and software modules, and guidelines for integrating parallel optical endpoints. Performance targets will follow the selected hardware and experimental requirements rather than a fixed channel count or data rate.

Suggested candidate profile

A background in electrical engineering, computer engineering, microelectronics or embedded systems would be suitable. Relevant preparation includes digital hardware design, FPGA development and embedded programming. Interest in high-speed interfaces, timing, data movement, device drivers and hardware–software co-design would support the project.

Research connections

Application Route · Starting September 2027

Apply with your profile and research interests. Your application is based on your academic profile, preparation and interests in the research topics.

No prior contact or agreement with a professor is required at the application stage. You do not need to approach a specific professor or obtain their approval before applying. Submit your letter of interest and the LPDP checklist materials through the portal.

No admission letter is needed to begin. TU Braunschweig handles academic assessment and admission as part of the selection process.

November 2026

Identify topics that fit your profile and interests.

Read the catalogue and consider how your academic background, experience and research interests connect with the proposed work.

November 2026

Prepare your application materials.

Provide your letter of interest and all materials required by the LPDP application checklist. Explain your preparation, motivation and interest in the topics.

01. Dezember 2026

Submit through the LPDP portal

Apply by 1 December 2026, 23:59 WIB (Western Indonesian Time) through the LPDP portal.

Think of it like applying for a position

The research topics describe the proposed work and the background that would help you succeed. Approach your application much as you would an application for a job: identify the topics that interest you, explain why your profile fits, and give concrete examples of what you have done and what you could contribute.

You are applying to be considered for the research opportunity; you do not need to arrange a place with a professor beforehand. Your letter of interest should make the connection between your experience, your motivation and the proposed research clear.

A strong letter of interest

Your preparation: show what you built, measured, designed or investigated in a previous project. Explain your own contribution and what you learned.
Your research interest: explain why a specific topic and its methods interest you, and connect your skills to the project's challenges.
Your contribution: connect the expertise you want to develop to a concrete need in Indonesia.

Write the letter yourself, in your own voice. All application documents are screened for the use of artificial intelligence (AI). Your letter should reflect your own experience, reasoning and motivation.

Scholarship and study support

LPDP provides scholarship support under its applicable award conditions. The exact personal benefits and payment amounts will be set out in the LPDP call and award documentation.

TU Braunschweig provides supervision, research infrastructure and materials, German language courses and coverage of the semester contribution.

Preparing for Braunschweig

Successful applicants will receive enrolment and arrival instructions. Health insurance, accommodation and residence arrangements should be planned before arrival.

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Check the Requirements

Apply by 1 December 2026

Why TU Braunschweig?

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Find the project that fits your strengths

Area 1: Semiconductor Materials and Devices

Area 2: Integrated Circuits and Computing Architectures

Area 3: Sensors and Electronic Systems

Application Route · Starting September 2027

Identify topics that fit your profile and interests.

Prepare your application materials.

Submit through the LPDP portal

Apply through the LPDP portal

Think of it like applying for a position

A strong letter of interest

Scholarship and study support

Preparing for Braunschweig