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  • Chair for Chip Design for Embedded Computing
  • Teaching
EIS der TU Braunschweig
ASIP-Lab
  • Teaching
    • Overview
    • Advanced FPGA-Design
    • Application-Specific Instruction-Set Processors (ASIP)
    • Memory Systems
    • Hardware-Praktikum
    • VLSI-Lab
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    • Verification, Validation and Testing of ASIC Designs
    • ASIP-Lab
    • Software-Entwicklungspraktikum: Smart-V

ASIP-Lab

Organization

  • This laboratory will be held in English.
  • This laboratory is intended for master's students.
  • The module Application-Specific Instruction-Set Processors is recommended as preparation for this course.

  • Entry in the official course directory
  • The laboratory takes place Friday 09:45 to 13:00 in the ChipdesignLab (Room IZ 261, 2nd floor, Mühlenpfordtstr. 23).

Description

The Lab teaches the concepts and architectures of specialized processors, the underlining theoretical concepts through the architecture modification of the Cadence LX7 processor.

After completing the module, the students are capable to

  • understand the concept of Application-Specific Instruction-Set Processors and how to use them

  • to specialize a basic processor architecture for an example out of domain of Advanced Driving Assist Systems

  • evaluate and assess an architecture for different optimization goals (e.g. maximum computing power or minimal power consumption) zu evaluieren und zu bewerten

Contents

  • Introduction to the architecture principles of processors and their specialization opportunities

  • Introduction to the architecture definitions of an Application-Specific Instruction-Set Processor, such as the LX7 processor architecture, and the extension possibilities of this ASIP

  • Introduction to custom extensions of instruction set of a processor, e.g. the Cadence LX7 processor, using Cadence Xtensa Explorer

  • Introduction to the hardware descrition language “Tensilica Instruction Extension”

  • Verification and Emulation of Processor architectures

Literature

  • Gries, M.; Keutzer, K.; "Building ASIPS: The Mescal Methodology", Springer, 2010

  • Leibson, S.: "Designing SOCs with Configured Cores. Unleashing the Tensilica Xtensa and Diamond Cores", Morgan Kaufmann, 2006

  • Henkel, J.; Parameswaran, S.:"Designing Embedded Processors", Springer, 2007

  • Nurmi, J.: "Processor Design. System-On-Chip Computing for ASICs and FPGAs", Springer, 2007

  • Flynn, M. J.; Luk, W.: "Computer System Design. System-on-Chip", Wiley, 2011

  • González, A.; Latorre, F.; Magklis, G.: "Processor Microarchitecture: An Implementation Perspective", Morgan&Claypool Publishers, 2010

  • Fisher, J.; Faraboschi, P.; Young, C.: "Embedded Computing: A VLIW Approach to Architecture, Compilers, and Tools", Morgan Kaufmann, 2005.

  • Hennessy, J.L.; Patterson, D. A.; "Computer Architecture: A Quantitative Approach", Morgan Kaufmann, 2011.

  • Leuppers, R.; Marwedel, P.: "Retargetable Compiler Technology for Embedded Systems: Tools and Applications", Springer, 2010

  • Jacob, B.; "The Memory System: You Can't Avoid It, You Can't Ignore It, You Can't Fake It", Morgan&Claypool Publishers, 2009

  • Kaxiras, S.: Martonosi, M.: "Computer Architecture Techniques for Power-Efficiency ", Morgan&Claypool Publishers, 2008

  • Olukotun, K.; Hammond, L.; Laudon, J.; "Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency ", Morgan&Claypool Publishers, 2007

  • Zaccaria, V.; Sami, M.G.; Silvano, C.: "Power Estimation and Optimization Methodologies for VLIW-based Embedded Systems", Springer, 2003

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