On Tuesday, 06.05.25 at 10:15 a.m. we invite you to the final presentation of the bachelor thesis of Mr. Mohamed Wassim Chebili in the seminar room of the C3E (262A). The topic of the bachelor thesis is “Design and Implementation of a Processor Core Architecture for Accelerated Logic Simulation”.

With the increasing complexity of VLSI systems, the importance and time required for verification continues to grow. This thesis deals with the design and implementation of a minimal and specialized processor architecture for accelerated execution of digital logic simulations on gate level. Based on the efficiently coded instruction execution of the NanoController architecture developed in the department, a suitable LUT-based processor data path is implemented. An exemplary gate netlist is used to verify the functionality of the architecture and an initial estimate of the hardware resources required for the ASIC implementation of the processor is made. The processor core can be used in further work as a building block for highly parallel logic simulation systems.