Moritz Weißbrich presents the NanoLogicController at ASAP 2026. The paper “NanoLogicController: A Minimal Open-Source ASIP for Accelerated Gate-Level Netlist Emulation” by Moritz Weissbrich, Mohamed Wassim Chebili, and Guillermo Payá-Vayá presents an approach for accelerating the verification of digital systems at netlist level, where increasing complexity challenges general-purpose processors and FPGA-based emulation.

The open-source ASIP uses a specialized data path and converts netlists into program code. In a post-synthesis evaluation using 22 nm FDSOI CMOS, the core architecture reached 6 GHz and required 3827 µm² including memories, providing a basis for a massively parallel manycore netlist emulator with up to approx. 250 cores/mm².