From October 8 to 10, 2025, the IEEE Cross-disciplinary Conference on Memory-Centric Computing (CCMCC 2025) took place in Dresden.

At the conference, Gia Bao Thieu presented his recent work titled “Design Space Exploration of a Direct Cached Memory Access Controller Optimized for HBM Memory Systems using TAPRE-HBM.”

The research was conducted in collaboration between the Chair for Chip Design for Embedded Computing (C3E) at TU Braunschweig and the Institute of Applied Microelectronics and Computer Engineering (Integrated Systems Group) at the University of Rostock.

The goal of this collaboration is to advance memory architectures for massively parallel processors and to optimize the interaction between processor and memory design.

By integrating High Bandwidth Memory (HBM) with a novel multi-port Direct Cached Memory Access (DCMA) architecture, the system efficiently utilizes the bandwidth of modern memory technologies. Using the FPGA-based TAPRE-HBM framework, the memory architecture was prototypically emulated and subjected to a comprehensive design space exploration.