Jasper Homann presented his research on the verification of configurable RISC-V processors at FSiC2025. In his talk, he introduced the use of the PATARA framework for automated test generation targeting the custom EIS-V (RISC-V) processor. Compared to official RISC-V test suites, PATARA achieves up to 100% VHDL code coverage.
The research is part of the DI-GATE-V project, funded by the BMFTR, which focuses on developing an open RISC-V processor family for GateMate FPGAs.