Jan Wagner

Diplom-Ingenieur (Dipl.-Ing.)
Wissenschaftlicher Mitarbeiter

Technische Universität Braunschweig
Abteilung Technische Informatik, E.I.S.
Mühlenpfordtstr. 23
D-38106 Braunschweig

Postfach 3329
D-38023 Braunschweig

Telefon +49 531/391-2387
+49 531/391-2376 (Sekretariat)
Fax +49 531/391-2375
E-Mail wagner {at} c3e.cs.tu-bs.de
Raum IZ 247


Journal Articles by J. Wagner

R. Meyer, J. Wagner, B. Farkas, S. Horsinka, P. Siegl, R. Buchty, and M. Berekovic
A Scriptable Standard-Compliant Reporting and Logging Framework for SystemC
ACM Trans. Embed. Comput. Syst., 16(1), 2016

Conference Papers

B. Farkas, S. A. A. Shah, J. Wagner, R. Meyer, R. Buchty, and M. Berekovic
An Open and Flexible SystemC to VHDL Workflow for Rapid Prototyping
Design and Verification Conference (DVCon) Europe 2016, October 19 - 20, 2016 Munich, Germany, 2016
RIS, BibTex
P. Siegl, R. Buchty, B. Farkas, S. A. Horsinka, R. Meyer, J. Wagner, and M. Berekovic
The Past, Present and Future of the Open-Source Virtual Platform SoCRocket
Workshop EMC2: Mixed Criticality Applications and Implementation Approaches, 2016
RIS, BibTex
R. Meyer, J. Wagner, R. Buchty, and M. Berekovic
Universal Scripting Interface for SystemC
DVCon Europe Conference Proceedings 2015, 2015
URL, RIS, BibTex
J. Wagner, R. Meyer, R. Buchty, and M. Berekovic
A scriptable, standards-compliant reporting and logging extension for SystemC
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, 2015
J. Wagner and R. Meyer
TLM Modeling for Space Applications
ACACES 2015 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, HiPEAC, 2015
PDF, RIS, BibTex
S. A. Horsinka, R. Meyer, J. Wagner, R. Buchty, and M. Berekovic
On RTL to TLM Abstraction to Benefit Simulation Performance and Modeling Productivity in NoC Design Exploration
NoCArc '14: Proceedings of the 2014 International Workshop on Network on Chip Architectures, ACM, 2014, ISBN 978-1-4503-3064-0
S. A. A. Shah, J. Wagner, T. Schuster, and M. Berekovic
A lightweight-system-level power and area estimation methodology for application specific instruction set processors
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2014 24th International Workshop on, 2014
DOI, RIS, BibTex
J. Wagner, R. Buchty, C. Schubert, and M. Berekovic
Designing a low-power wireless sensor node rASIP architecture
Signal Processing Systems (SiPS), 2013 IEEE Workshop on, 2013
DOI, RIS, BibTex

  aktualisiert am 25.02.2015
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